Storage efficient sliding window sum
AssigneeUTStarcom, Inc.
InventorsCindy Wang, Xiangyang Xu, Xiaochun Chen
Life of this patent
Estimating the term…
Abstract
A delay buffer includes a first shift register receiving input data and having a shift signal input port. The first shift register right shifts the input data responsive to a shift signal on the shift signal input port. The shift signal is determined based on an effective bit width of the input data. A first delay line receives the shifted data from the first shift register while a second delay line of equal length to the first delay line receives the shift signal. A second shift register receives the output from the first delay line and receives the output of the second delay line on a shift signal input port. The second shift register then left shifts the data contained therein according to the shift signal.
Claims4
A delay buffer comprising:
- a first shift register receiving input data and having a shift signal input port, the first shift register operable to shift the input data responsive to a shift signal on the shift signal input port;
- means for determining an effective bit width of the input data, said determining means providing a shift signal to the first shift register shift signal input port;
- a first delay line receiving the shifted data from the first shift register;
- a second delay line of equal length to the first delay line receiving the shift signal;
- and
- a second shift register receiving the output from the first delay line and having a shift signal input port receiving the output of the second delay line, the second shift register shifting the data contained therein according to the shift signal.
Dependencies are inferred from the claim text.