Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface
AssigneeFreescale Semiconductor, Inc.
InventorsMahibur Rahman, Emilio Quiroga
Life of this patent
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Abstract
Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles of the common clock signal. One of the plurality of phases is selected (308) for each of the serial bitstreams based upon the activity detected within the selected phase. Data is then extracted (322) from the selected phase for each of the serial bitstreams using the common clock signal to thereby bit synchronize each of the plurality of serial bitstreams to each other.
Claims21
A method for bit synchronizing a plurality of serial bitstreams with a common clock signal, the method comprising the steps of:
- detecting activity occurring within each of a plurality of phases for each of the serial bitstreams, wherein each of the plurality of phases corresponds to a cycle of the common clock signal;
- selecting one of the plurality of phases for each of the serial bitstreams based upon the activity detected within the selected phase;
- and
- extracting data from the selected phase for each of the serial bitstreams to thereby bit synchronize each of the plurality of serial bitstreams.
A device for synchronizing one of a plurality of serial bitstreams to the other bitstreams received in a multi-pin asynchronous interface having a common clock signal, the device comprising:
- an activity detection module configured to detect bit transitions occurring during each of a plurality of phases of the bitstream, each phase corresponding to a cycle of the common clock signal;
- a phase selection module coupled to the activity detection module and configured to select one of the plurality of phases based upon the bit transitions detected within each of the plurality of phases;
- and
- a data extraction module coupled to the phase selection module, wherein the data extraction module is configured to extract the selected phase of the bitstream to thereby bit synchronize the bitstream to the other serial bitstreams.
A system for synchronizing a plurality of serial bitstreams having a common bitrate that are each received at a multi-pin asynchronous interface, the system comprising:
- a clock generator configured to produce a common clock signal having a frequency substantially equal to an integer multiple of the common bitrate;
- a plurality of bit synchronization modules each associated with one of the plurality of serial bitstreams configured to receive the common clock signal, each of the plurality of bit synchronization modules comprising:
- an activity detection module configured to detect bit transitions occurring during each of a plurality of phases of the associated bitstream, each phase corresponding to a cycle of the common clock signal;
- a phase selection module coupled to the activity detection module and configured to select one of the plurality of phases based upon the bit transitions detected within each of the plurality of phases;
- and
- a phase extraction module coupled to the phase selection module, wherein the phase extraction module is configured to extract the selected phase of the associated bitstream to thereby bit synchronize the associated bitstream to the other serial bitstreams;
- and
- a word synchronization module configured to receive each of the extracted bitstreams from the plurality of bit synchronization modules and to extract data words from the synchronized bitstreams.
Dependencies are inferred from the claim text.