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US 2006/0222134 A1Published application
Data cleaning with an asynchronous reference clock
AssigneeSilicon Laboratories Inc.
InventorsAdam Eldredge, Yunteng Huang
Life of this patent
Estimating the term…
Abstract
Embodiments of the present invention may provide for independent setting of jitter tolerance and jitter transfer levels, and reduced jitter generation of a data transmission device, such as a clock and data recovery (CDR) circuit or the like. An architecture may provide for reconfigurability of a circuit for use in various applications. The architecture may include a multi-loop structure, such as a tri-loop structure.
Claims26
An apparatus comprising:
- a first loop to receive incoming data and to generate a sampling clock signal;
- a second loop to generate a retiming clock signal based on an input reference signal;
- and
- a third loop coupled to supply a control signal to control the second loop.
1 more element
A clock and data recovery (CDR) circuit comprising:
- a CDR loop to receive incoming data and recover a data signal and a sampling clock signal therefrom;
- and
- a clock generation loop coupled to the CDR loop to provide a retiming clock signal to the CDR loop, the retiming clock signal generated independently of the sampling clock signal.
A method comprising:
- receiving an incoming signal and recovering data and a sampling clock from the incoming signal in a first loop;
- generating a retiming clock independently of the sampling clock;
- and
- transmitting the data using the retiming clock.
1 more element
A system comprising:
- a framer to serialize incoming data into a data signal;
- a clock and data recovery (CDR) loop coupled to receive the data signal;
- and
- a clock generation loop coupled to the CDR loop to provide a retiming clock signal to the CDR loop using a fractional N-divider.
1 more element
Dependencies are inferred from the claim text.