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US 2006/0222132 A1Published application
Receive timing manager
AssigneeTexas Instruments Incorporated
InventorsDenis Beaudoin, Ritesh Sojitra, Gregory Christison
Life of this patent
Estimating the term…
Abstract
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
Claims35
A receive timing manager comprising:
- a data node;
- an edge detection logic coupled to the data node;
- a data selection logic coupled to the edge detection logic;
- a plurality of data flip-flops each having an input node, a clock node and an output node;
- and
- a multiplexer coupled to the data flip-flops and the data selection logic.
3 more elements
An edge detection logic circuit comprising:
- a data node;
- a plurality of delay buffers each having an input node and an output node wherein the delay buffers are coupled in series and wherein the input node of the first delay buffer is coupled to a clock;
- a plurality of delay clock nodes each coupled to the output node of one of the delay buffers;
- a plurality of two-stage-sync devices each having a clock node, an input node and an output node wherein the clock node is coupled to one of the delay clock nodes, and the input node is coupled to the data node;
- and
- a plurality of XOR gates each having a first input node, a second input node and an output node wherein the first input node is coupled to the output node of one of the two-stage-sync devices, the second input node is coupled to the output node of the next two-stage-sync device.
3 more elements
An edge detection logic circuit comprising:
- a first clock node;
- a second clock node;
- a plurality of delay buffers each have an input node and an output node wherein the delay buffers are coupled in series and wherein the input node of the first delay buffer is coupled to the second clock node;
- a plurality of delay clock nodes each coupled to an output node of one of the delay buffers;
- a plurality of synchronizers each having a first input node, a second input node and an output node wherein the first input node is coupled to one of the delay clock nodes, and the second input node is coupled to the first clock node;
- a plurality of first NAND gates each having a first input node, a second input node and an output node wherein the first input node is coupled to an inverse node of the output node of one of the synchronizers, the second input node is coupled to the output node of the next synchronizer;
- a plurality of second NAND gates each having a first input node, a second input node and an output node wherein the first input node is coupled to an inverse node of the output node of one of the synchronizer, the second input node is coupled to the output node of the previous synchronizer;
- a plurality of rising-edge registers each is coupled to the output nodes of a group of neighboring first NAND gates and each rising-edge register is coupled in series;
- and
- a plurality of falling-edge registers each is coupled to the output nodes of a group of neighboring second NAND gates and each falling-edge register is coupled in series.
7 more elements
A data dragging logic circuit comprising:
- a first flip-flop having its clock end coupled to a first clock node, its input end coupled to the data node;
- a second flip-flop having its clock end coupled to a second clock node and its input end coupled to the output end of the first flip-flop;
- a multiplexer having a first input node coupled to the output node of the first flip-flop and a second input node coupled to the output node of the second flip-flop;
- and
- a third flip-flop having its clock end coupled to a third clock node, its input end coupled the output end of the multiplexer.
2 more elements
A method of selecting an optimal sample point of a received data, the method comprising:
- selecting a sample window;
- taking a plurality of samples in the sample window;
- finding a transition point;
- and
- selecting an optimal sample point away from the transition point.
2 more elements
A method of finding a data transition point, the method comprising:
- creating a plurality of delayed clocks from a system clock;
- sampling a plurality of samples wherein each sample is taken at one of the delayed clocks;
- and
- comparing each sample with a sample taken at the next delay to find the data transition points.
1 more element
A method of finding clock rising and falling edges, the method comprising:
- creating a plurality of delayed clocks from a system clock;
- sampling a plurality of samples from the system clock wherein each sample is taken at one of the delayed clocks;
- comparing each sample with a sample taken at the next delayed clock to find the rising edge;
- storing a group of rising-edge information into one of plurality of rising-edge registers wherein the rising-edge registers are coupled in series;
- comparing each sample with a sample taken at the next delay to find the falling edge;
- and
- storing a group of falling-edge information into one of plurality of falling-edge registers wherein the falling-edge registers are coupled in series.
4 more elements
A method of dragging a sample back to a reference clock comprising the steps of:
- sampling a data at a sample point from a node to form a first sample;
- re-sampling the first sample at the next clock cycle;
- dividing the sample point by an integer to form a fraction value;
- and
- repeating re-sampling the new sample obtained in the previous step at a new point of the next clock cycle wherein the new point equals a previous sample point minus the fraction value to get a new sample.
2 more elements
A circuit for selecting an optimal sample of a received data, the circuit comprising:
- means for selecting a sample window;
- means for taking a plurality of samples in the sample window;
- means for finding a transition point;
- means for selecting an optimal sample point away from the transition point;
- and
- means for selecting an optimal sample at the optimal sample point.
3 more elements
A receive timing manager comprising:
- an edge detection circuit coupled to a data node and having an output related to a detected edge of a signal at the data node;
- and
- a selection circuit configured to store a plurality of time shifted samples of the signal at the data node, the selection circuit outputting a first sample that is one of the time shifted samples based upon a value of the output of the edge detection circuit.
Dependencies are inferred from the claim text.