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US 2006/0222000 A1Published application
Decoder architecture systems, apparatus and methods
AssigneeIntel Corporation
InventorsEric Vannerson, Kalpesh Mehta, Louis Lippincott
Life of this patent
Estimating the term…
Abstract
An embodiment includes an apparatus that includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.
Claims22
An apparatus comprising:
- a variable length decoder to receive a compressed bit stream that is based on a coding standard, wherein the variable length decoder includes,
- a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard;
- and
- a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.
1 more element
A method comprising:
- receiving encoded data that is encoded using a coding standard;
- decoding, using a hardware accelerator of a decoder, the encoded data that is based on an operation that is common across multiple coding standards that includes the coding standard;
- and
- decoding, using a programmable element of the decoder, the encoded data that is based on an operation that is unique to the coding standard.
1 more element
A system comprising:
- a Static Random Access Memory (SRAM);
- and
- a variable length decoder to receive a compressed bit stream that is encoded based on a coding standard, wherein the variable length decoder includes,
- a hardware accelerator to perform a decode operation that includes an operation to locate a start code in the compressed bit stream, wherein the decode operation is common to multiple coding standards that includes the coding standard;
- and
- a programmable element to receive an output from the decode operation and to perform an operation that is unique to the coding standard, wherein the programmable element is to store a result of the operation that is unique to the coding standard into the SRAM and to generate a first set of decoded data based on the compressed bit stream;
- and
- a hardware accelerator to perform a decode operation that is common across multiple coding standards to generate a second set of decoded data based on the compressed bit stream, wherein the multiple coding standards includes the coding standard, wherein the hardware accelerator is to store the first set of decoded data and the second set of decoded data in the SRAM.
5 more elements
A method comprising:
- controlling a hardwired element to forward a number of bits of a received compressed bit stream;
- deriving sequence level data from the compressed bit stream;
- deriving frame level data from the compressed bit stream;
- and
- controlling the hardwired element to perform a decode operation of macroblocks of data from the received compressed bit stream.
2 more elements
Dependencies are inferred from the claim text.