Differential delay compensation
AssigneeIntel Corporation
InventorsJing Ling, Soowan Suh, Juan-Carlos Calderon
Life of this patent
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Abstract
In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
Claims20
A method, comprising:
- receiving a plurality of data frames representing at least one virtually concatenated data stream;
- storing the plurality of data frames in a memory;
- and
- recording, for each of the plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
A computer program product comprising logic instructions stored on a computer-readable medium which, when executed by a processor, configure the processor to:
- receive a plurality of data frames representing at least one virtually concatenated data stream;
- store the plurality of data frames in a memory;
- and
- record, for each of the plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
An apparatus, comprising:
- a receiver to receive a plurality of data frames representing at least one virtually concatenated data stream;
- and
- a processor to:
- store the plurality of data frames in a memory;
- and
- record, for each of the plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
A system, comprising:
- a first line card;
- a backplane interface;
- a second line card communicatively coupled to the first line card via the backplane interface and comprising a processor capable to:
- store a plurality of received data frames in a memory;
- and
- record, for each of the plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
Dependencies are inferred from the claim text.