Circuit and method for operating a delay-lock loop in a power saving manner

A memory device, comprising:

• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;
• a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;
• a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• a delay-lock loop operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the delay-loop comprising a delay line receiving a reference clock signal and generating an output clock signal from which either the write data strobe signal or the read data strobe signal is derived, the delay-lock loop further comprising a phase detector receiving the reference clock signal and the output clock signal and controlling the delay of the delay line responsive thereto;
• and
• a loop control circuit selectively coupling the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a normal operating mode to continuously couple the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a standby mode to enter a standby period in which the reference clock signal is isolated from the delay line, and, while in the standby period, periodically couple the reference clock signal to the delay line for an update period of sufficient duration to allow the delay-lock loop to achieve a locked condition.

A memory device, comprising:

• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;
• a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;
• a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• a delay-lock loop operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the delay-loop comprising a delay line receiving a reference clock signal and generating an output clock signal from which either the write data strobe signal or the read data strobe signal is derived, the delay-lock loop further comprising a phase detector receiving the reference clock signal and the output clock signal and controlling the delay of the delay line responsive thereto;
• and
• a loop control circuit selectively coupling the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a normal operating mode to continuously couple the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a standby mode to enter a standby period in which the reference clock signal is isolated from the delay line, and, while in the standby period, periodically couple the reference clock signal to the delay line for an update period of sufficient duration to allow the delay-lock loop to achieve a locked condition.

A processor-based system, comprising

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a memory device coupled to the processor bus adapted to allow data to be stored, the memory device comprising:
• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;
• a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;
• a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• a delay-lock loop operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the delay-loop comprising a delay line receiving a reference clock signal and generating an output clock signal from which either the write data strobe signal or the read data strobe signal is derived, the delay-lock loop further comprising a phase detector receiving the reference clock signal and the output clock signal and controlling the delay of the delay line responsive thereto;
• and
• a loop control circuit selectively coupling the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a normal operating mode to continuously couple the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a standby mode to enter a standby period in which the reference clock signal is isolated from the delay line, and, while in the standby period, periodically couple the reference clock signal to the delay line for an update period of sufficient duration to allow the delay-lock loop to achieve a locked condition.

A processor-based system, comprising

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a memory device coupled to the processor bus adapted to allow data to be stored, the memory device comprising:
• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;
• a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;
• a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• a delay-lock loop operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the delay-loop comprising a delay line receiving a reference clock signal and generating an output clock signal from which either the write data strobe signal or the read data strobe signal is derived, the delay-lock loop further comprising a phase detector receiving the reference clock signal and the output clock signal and controlling the delay of the delay line responsive thereto;
• and
• a loop control circuit selectively coupling the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a normal operating mode to continuously couple the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a standby mode to enter a standby period in which the reference clock signal is isolated from the delay line, and, while in the standby period, periodically couple the reference clock signal to the delay line for an update period of sufficient duration to allow the delay-lock loop to achieve a locked condition.