US 2006/0221754 A1Published application

Semiconductor memory device

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorsWataru Abe, Mituaki Hayashi, Shuji Nakaya

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Abstract

In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low voltage. A sub-bit line SBL in a subarray 12 is connected via a first transistor PC1 to a power source voltage, and via a second transistor NC1 to a ground voltage. A main bit line MBLj is connected via a third transistor PD1 to the power source voltage. The gate electrodes of the first transistor PC1 and the second transistor NC1 are connected to the main bit line MBLj, the gate electrode of the third transistor PD1 is connected to the sub-bit line SBL. In an initial state, a voltage of the main bit line MBLj is controlled to be at an H level, and voltages of word lines WLi1 to Wlip are controlled to be at an L level. When a read operation is performed, the voltage of the main bit line MBLj transitions to the L level, and thereafter, the voltage of a selected word line transitions to the H level.

Claims28

Dependent claims

A semiconductor memory device with a hierarchical bit line structure, comprising:

a plurality of subarrays arranged in a row direction and a column direction;
a plurality of word lines connected to the subarrays placed on the respective same rows;
a plurality of main bit lines connected to the subarrays placed on the respective same columns;
a row decoder for selecting one of the word lines, based on a given row address;
a column decoder for selecting one of the main bit lines, based on a given column address;
and
a main bit line control circuit for controlling the main bit line selected by the column decoder,
wherein the subarray includes:
a sub-bit line;
a first switch section for switching whether or not the sub-bit line is connected to a power source voltage;
a second switch section for switching whether or not the sub-bit line is connected to a ground voltage;
a third switch section for switching whether or not the main bit line is connected to a predetermined power source, based on a voltage of the sub-bit line;
and
a plurality of memory cells for applying an influence depending on data stored therein, onto the sub-bit line, when a corresponding one of the word lines is selected.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/378,384Filed 20 Mar 2006
Priority: JP 2005-10306031 Mar 2005
Published: 5 Oct 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 2207/002
Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store: isolation gates, i.e.…
G11C
Static stores