Memory chip architecture with high speed operation
AssigneeHynix Semiconductor Inc.
InventorsGeun-Il Lee, Yong-Suk Joo
Life of this patent
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Abstract
A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.
Claims19
A semiconductor memory device comprising:
- at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device;
- a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device;
- a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address;
- and
- at least one bank area, arranged between the global line block and the data transmission block, each bank area containing a plurality of data I/O blocks located closer to the data transmission block than the global line blocks and a plurality of control blocks located closer to the global line block than the data transmission block.
A semiconductor memory device comprising:
- a top bank area having a plurality of top banks, the top bank area arranged above a virtual bisector, wherein the virtual bisector divides a minor-axis of the semiconductor memory device;
- a bottom bank area having a plurality of bottom banks, the bottom bank area arranged below the virtual bisector;
- a plurality of first data I/O pads arranged in a top margin of the top bank area;
- a plurality of second data I/O pads arranged in a bottom margin of the bottom bank area;
- and
- a control line block, arranged between the top bank area and the bottom bank area in a direction of the virtual bisector, for transmitting inputted command and address,
- wherein one half of data corresponding to the inputted command and address are outputted through the plurality of first data I/O pads and another half of the data are outputted through the plurality of second I/O pads.
Dependencies are inferred from the claim text.