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US 2006/0221746 A1Published application
Pseudo SRAM
AssigneeHynix Semiconductor Inc.
InventorsHee-Bok Kang, Jin-Hong Ahn
Life of this patent
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Abstract
A unit memory cell for use in a pseudo static random access memory (SRAM) includes a cell capacitor; a normal accessing transistor whose gate, drain and source are respectively connected to a normal accessing word line, a normal accessing bit line and a storage node of the cell capacitor; and a refresh accessing transistor whose gate, drain and source are respectively connected to a refresh accessing word line, a refresh accessing bit line and the storage node of the cell capacitor.
Claims8
A unit memory cell for use in a pseudo static random access memory (SRAM), comprising:
- a cell capacitor;
- a normal accessing transistor whose gate, drain and source are respectively connected to a normal accessing word line, a normal accessing bit line and a storage node of the cell capacitor;
- and
- a refresh accessing transistor whose gate, drain and source are respectively connected to a refresh accessing word line, a refresh accessing bit line and the storage node of the cell capacitor.
1 more element
A pseudo SRAM, comprising:
- a memory cell array block where a plurality of normal accessing bit lines and refresh accessing bit lines and a plurality of normal accessing word lines and refresh accessing word lines are arranged in pairs, wherein the memory cell array block includes a unit memory cell, the unit memory cell including:
- a cell capacitor;
- a normal accessing transistor for selectively connecting the cell capacitor to the normal accessing bit line under the control of the normal accessing word line;
- and
- a refresh accessing transistor for selectively connecting the cell capacitor to the refresh accessing bit lines under the control of the refresh accessing word line;
- a normal accessing sense amplifier array block which is arranged on one column side of the memory cell array block and is connected to the normal accessing bit line;
- a refresh accessing sense amplifier array block which is arranged on the other column side of the memory cell array block and is connected to the refresh accessing bit line;
- a normal accessing local data bus connected to the normal accessing sense amplifier array block;
- and
- a refresh accessing local data bus connected to the refresh accessing sense amplifier array block.
7 more elements
Dependencies are inferred from the claim text.