Refresh circuit for use in semiconductor memory device and operation method thereof
AssigneeHynix Semiconductor Inc.
InventorIhl-Ho Lee
Life of this patent
Estimating the term…
Abstract
A refresh circuit for individually performing a refresh operation to a plurality of banks included in a semiconductor memory device, includes: a perbank counter for generating a refresh bank address according to a refresh pulse signal and a perpank command; a perbank multiplexer for selectively outputting one of the refresh bank address and a data access bank address in response to the perbank command; and an internal command state machine for generating a refresh command in response to the refresh pulse signal and the perbank command.
Claims12
A refresh circuit for individually performing a refresh operation to each of a plurality of banks included in a semiconductor memory device, comprising:
- a perbank counter for generating a refresh bank address according to a refresh pulse signal and a perpank command;
- a perbank multiplexer for selectively outputting one of the refresh bank address and a data access bank address in response to the perbank command;
- and
- an internal command state machine for generating a refresh command in response to the refresh pulse signal and the perbank command.
A refresh method for performing a refresh operation to a selected bank among a plurality of banks included in a semiconductor memory device, comprising the steps of:
- generating a refresh bank address according to a refresh pulse signal and a perpank command;
- selectively outputting one of the refresh bank address and a data access bank address in response to the perbank command;
- and
- generating a refresh command in response to the refresh pulse signal and the perbank command.
Dependencies are inferred from the claim text.