Semiconductor memory device

Abstract

A memory device conducts a stable data access operation by removing glitch component in an internal clock outputted after a completion of self-refresh. This memory device comprises a memory core region, a clock enable sensor for sensing an enable of a clock enable signal corresponding to a termination of a self-refresh operation to provide a sensing signal, a clock buffer for buffering a clock signal from the outside as an internal clock signal in response to the sensing signal and providing the internal clock signal to the memory core region, and a self-refresh control circuit for preventing a glitch component in the internal clock signal firstly outputted by the clock buffer in response to the sensing signal from transferring to the memory core region.

Dependencies are inferred from the claim text.