Semiconductor wafer and method for testing ferroelectric memory device
AssigneeSeiko Epson Corporation
InventorAkihito Matsumoto
Life of this patent
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Abstract
A semiconductor wafer includes a plurality of semiconductor chip regions including ferroelectric memory devices, a test chip region, and a wiring that connects each of the plurality of semiconductor chip regions with the test chip region.
Claims16
A semiconductor wafer comprising:
- a plurality of semiconductor chip regions including ferroelectric memory devices;
- a test chip region;
- and
- a wiring that connects each of the plurality of semiconductor chip regions with the test chip region.
A method for testing a ferroelectric memory device in a semiconductor wafer that includes a plurality of semiconductor chip regions including ferroelectric memory devices, a test chip region, and a wiring that connects each of the plurality of semiconductor chip regions with the test chip region, the method comprising applying a test control signal and a test pulse signal from the test chip region to each of the plurality of semiconductor chip regions through the wiring.
Dependencies are inferred from the claim text.