Semiconductor integrated circuit device and inspection method of the same
AssigneeNEC Electronics Corporation
InventorHiroyuki Kobatake
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit device includes: a plurality of memories and a judgement circuit. Each of plurality of memories is configured to include a Built-in Self Test (BIST) circuit that examines a possibility of repairing a defect and outputs a repair possibility signal indicating the possibility. The judgement circuit is configured to judge whether or not all of the plurality of memories can be repaired based on a plurality of the repair possibility signals. Each of the plurality of the repair possibility signals is outputted from one of the plurality of memories.
Claims20
A semiconductor integrated circuit device comprising:
- a plurality of memories, each of which is configured to include a Built-in Self Test (BIST) circuit that examines a possibility of repairing a defect and outputs a repair possibility signal indicating said possibility;
- and
- a judgement circuit configured to judge whether or not all of said plurality of memories can be repaired based on a plurality of said repair possibility signals, each of which is outputted from one of said plurality of memories.
A semiconductor integrated circuit device comprising:
- a plurality of function blocks configured to be provided on a chip;
- a plurality of memories, each of which is configured to be included in one of said plurality of function blocks;
- and
- a judgement circuit configured to be connected to said plurality of memories,
- wherein each of said plurality of memories includes a Built-in Self Test (BIST) circuit that examines a possibility of repairing a defect and outputs a repair possibility signal indicating said possibility;
- and
- said judgement circuit judges whether or not all of said plurality of memories can be repaired based on a plurality of said repair possibility signals, each of which is outputted from one of said plurality of memories.
A inspection method of a semiconductor integrated circuit device, comprising:
- (A) providing a semiconductor integrated circuit device which includes a plurality of memories, wherein each of said plurality of memories includes a Built-in Self Test (BIST) circuit that examines a possibility of repairing a defect and outputs a repair possibility signal indicating said possibility;
- (B) Activating said BIST circuit included in all of said plurality of memories;
- and
- (C) judging whether or not said semiconductor integrated circuit device can be repaired based on a plurality of said repair possibility signals, each of which is outputted from one of said plurality of memories.
Dependencies are inferred from the claim text.