Repair control circuit of semiconductor memory device with reduced size

A semiconductor memory device comprising:

• a first decoder configured to control at least a program operation of the semiconductor memory device;
• a repair control circuit includes:
• a flash cell decoder configured to generate a program control signal or a read control signal and word line bias voltages in response to:
• a cell program signal and address signals corresponding to fail cells, or
• a cell read signal and input address signals;
• a flash cell box configured to execute a program operation or a read operation in response to the program control signal or the read control signal and the word line bias voltages, wherein in the program operation, address signals corresponding to the fail cells are programmed, and redundancy control signals are output in the read operation;
• and
• a control signal generator configured to output a decoder select signal in response to the redundancy control signals.