Data output buffer whose mode switches according to operation frequency and semiconductor memory device having the same

A semiconductor memory device, comprising:

• a memory array including a plurality of memory cells arranged in a matrix formed by rows and columns;
• an X-decoder for decoding a certain row address and, selecting a row of the memory array;
• an Y-decoder for decoding a certain column address and, selecting a column of the memory array;
• and
• a data output buffer adapted to output data of a buffer input line read from a memory cell of the memory array specified by the X-decoder and the Y-decoder to a buffer output line, the provision of data from the buffer input line to the buffer output line being blocked in response to a reference control signal, and being prevented from being blocked when a period of the reference control signal is shorter than a reference period.

A data output buffer for providing data which are received from a buffer input line, to a buffer output line, the data output buffer comprising:

• a delay control unit adapted to generate a buffer enable signal in response to a received reference control signal;
• and
• a buffer unit adapted to provide the data of the buffer input line to the buffer output line in response to the buffer enable signal being activated, and to block provision of the data to the buffer output line in response to the buffer enable signal being deactivated,
• wherein when a period of the reference control signal is longer than a reference period, then the buffer enable signal transitions to an activated state in response to the reference signal transitioning to a first logic level, and transitions to a deactivated state in delayed response to the reference signal transitioning to a second logic level, and
• wherein when a period of the reference control signal is shorter than a reference period, then the buffer enable signal remains in an activated state.