Semiconductor memory card, semiconductor memory control apparatus, and semiconductor memory control method

A semiconductor memory card used by being connected to an access unit, comprising:

• a host interface section which sends a control signal and data to said access unit and receives a signal from said access unit;
• a nonvolatile memory which includes a plurality of nonvolatile memory chips and in which a plurality of continuous sectors is grouped to be a block as a minimum unit of data erasing;
• a memory controller which is connected to each of said plurality of nonvolatile memory chips with respectively independent bidirectional buses and controls erasing, writing, and reading of data;
• and
• a host information memory which temporarily stores a write speed mode given by said access unit, wherein
• said memory controller includes a nonvolatile memory access section which performs writing with respect to said plurality of nonvolatile memory chips with controlling write timing to each of said plurality of nonvolatile memories depending on a speed mode stored in said host information memory.

A semiconductor memory control apparatus used by being connected to a nonvolatile memory which includes a plurality of nonvolatile memory chips in which a plurality of continuous sectors is grouped to be a block as a minimum unit of data erasing:

• a host interface section which sends a control signal and data to an access unit and receives a signal from said access unit;
• a memory controller which is connected to each of said plurality of nonvolatile memory chips with respectively independent bidirectional buses and controls erasing, writing, and reading of data;
• and
• a host information memory which temporarily stores a write speed mode given by said access unit, wherein
• said memory controller includes a nonvolatile memory access section which performs writing with respect to said plurality of nonvolatile memory chips with controlling write timing to each of said plurality of nonvolatile memories depending on the speed mode stored in said host information memory.