Decoding circuit for non-binary groups of memory line drivers

An integrated circuit comprising:

• a memory array comprising a plurality of array lines;
• a non-binary number of array line driver circuits coupled with the plurality of array lines;
• and
• a decoder circuit coupled with the non-binary number of array line driver circuits, the decoder circuit comprising:
• a binary decoder;
• and
• circuitry operative to perform a non-binary arithmetic operation,
• wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder.

An integrated circuit comprising:

• a memory array comprising a plurality of array lines;
• a plurality of groups of array line driver circuits coupled with the plurality of array lines;
• a number of array line driver circuits in at least one of the plurality of groups of array line driver circuits, wherein the number is other than an integral power of two;
• and
• control circuitry configured to select one of the array line driver circuits.