Nonvolatile semiconductor memory device and manufacturing method of the same
AssigneeSanyo Electric Co., Ltd.
InventorMasahiro Obuchi
Life of this patent
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Abstract
The invention realizes a smaller-sized OTP memory cell and large reduction of its manufacturing process and cost. An embedded layer (BN+) to be a lower electrode of a capacitor is formed in a drain region of a cell transistor of an OTP memory, a capacitor insulation film having a small thickness where dielectric breakdown can occur by a predetermined voltage applied from a data line is formed on this embedded layer, and a conductive layer to be an upper electrode of a capacitor is formed on the capacitor insulation film and on a field oxide film. The embedded layer (BN+) partially overlaps a high concentration drain region (N+).
Claims14
A nonvolatile semiconductor memory device comprising:
- a plurality of word lines;
- a plurality of data lines;
- a plurality of memory cells formed on a semiconductor substrate, each of the memory cells comprising a transistor and a capacitor, the transistor comprising a drain region, a source region and a gate electrode connected with a corresponding word line, the capacitor comprising an impurity-implanted lower electrode formed in the drain region, an insulation film disposed on the lower electrode and an upper electrode disposed on the insulation film and connected with a corresponding data line;
- and
- a voltage supply circuit applying a voltage to the data lines,
- wherein the insulation film is configured to break down when a predetermined voltage is applied to the insulation film through a corresponding data line so that a predetermined data is written in the memory device.
A method of manufacturing a nonvolatile semiconductor memory device, comprising:
- providing a semiconductor substrate;
- forming a first impurity region in the substrate;
- forming an insulation film on the first impurity region;
- forming a second impurity region in the first impurity region;
- forming a conductive layer on the insulation film so that the second impurity region, the insulation film and the conductive layer form a capacitor;
- and
- forming a transistor comprising the first impurity region as a drain region so that the transistor and the capacitor form a memory cell.
A method of manufacturing a nonvolatile semiconductor memory device, comprising:
- providing a semiconductor substrate;
- forming an element isolation film in the substrate;
- ion-implanting impurities into the substrate so as to form a drain region adjacent the element isolation film and to form a source region;
- forming a first insulation film on the substrate;
- patterning the first insulation film so as to form a gate insulation film;
- forming a second insulation film on the drain region;
- ion-implanting impurities into the drain region so as to form a lower electrode;
- forming a gate electrode on the gate insulation film;
- forming an upper electrode on the second insulation film and the element isolation film so that the upper and lower electrodes and the second insulation film form a capacitor;
- and
- ion-implanting impurities into the source and drain regions using the gate electrode and the upper electrode as a mask so as to form a transistor comprising the source and drain regions, the gate insulation film and the gate electrode.
Dependencies are inferred from the claim text.