Use of data latches in multi-phase programming of non-volatile memories
AssigneeSanDisk Corporation
InventorsYan Li, Raul-Adrian Cernea
Life of this patent
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Abstract
A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.
Claims17
A non-volatile memory device, comprising:
- one or more memory cells each capable of storing N bits of data, where N is greater than or equal to one;
- and
- read/write circuitry connectable to the memory cells, comprising:
- programming circuitry to apply a monotonically non-decreasing programming waveform to the memory cells;
- bias circuitry to set bias conditions in the memory cells concurrently with the programming waveform being applied to the memory cells, wherein a first set of bias conditions is used during a first programming phase and a second set of bias conditions is used during a second programming phase;
- and
- one or more sets of latches each associated with a corresponding one of the memory cells to which the read/write circuitry is connected, wherein a first latch of each of said sets of latches governs which of the programming phases is active.
Dependencies are inferred from the claim text.