Page buffer circuit of flash memory device
AssigneeHynix Semiconductor Inc.
InventorDuck Kim
Life of this patent
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Abstract
A page buffer circuit of a flash memory device includes a plurality of page buffers connected to a predetermined number of bit lines, respectively, and also connected to a Y-gate circuit, the page buffers perform a read operation or a program operation at the same time in response to bit line control signals, bit line select signals and control signals. Each of page buffers included in a page buffer circuit selectively gains access to one of memory cells connected to a predetermined number of bit lines, respectively. As a result, coupling capacitance component between sensing nodes can be reduced and the overall chip size can be reduced.
Claims11
A flash memory device, comprising:
- a plurality of page buffers coupled to a predetermined number of bit lines that are coupled to a sensing node to reduce coupling capacitance, each page buffer coupled to a Y-gate circuit, and configured to perform a read operation or a program operation at substantially the same time in response to bit line control signals, bit line select signals, and control signals,
- wherein each of the plurality of page buffers is configured to:
- store sensing data corresponding to read data that are received from one of the predetermined number of bit lines,
- output the stored sensing data to the Y-gate circuit during the read operation,
- store program data that are received from the Y-gate circuit, and
- output the stored program data to one of the predetermined number of bit lines during the program operation.
A control method for a read operation of a page buffer circuit of a flash memory device, comprising:
- selecting a bit line from a plurality of bit lines that are coupled to a sense node using a bit line select circuit of given page buffer from a plurality of page buffers that are coupled to the bit lines, respectively, and Y-gates to connect the selected bit line to a sensing node;
- separating the remaining bit lines other than the selected bit line from the sensing node using the bit line select circuit to apply a bit line bias voltage to the remaining bit lines;
- sensing a voltage of the sensing node using a sensing circuit of each of the plurality of page buffers to generate sensing data, the voltage corresponding to read data from the selected bit line;
- latching and inversing the sensing data using a latch circuit of each of the plurality of page buffers and outputting the latched inversed data;
- and
- outputting the latched inversed data to one of the Y-gates in response to an I/O control signal using a switch of each of the plurality of page buffers.
A control method for a program operation of a page buffer circuit of a flash memory device, comprising the steps of:
- receiving and outputting program data from one of the Y-gates in response to an I/O control signal using a first switch of each of a plurality of page buffers that are coupled to a predetermined number of bit lines, respectively, and are coupled to Y-gates, respectively;
- latching the program data received from the first switch using a latch circuit of each of the plurality of page buffers;
- selecting one of the predetermined number of bit lines coupled to a sensing node and coupling the selected bit line to the sensing node using a bit line select circuit of each of the plurality of page buffers;
- decoupling the remaining bit lines other than the selected bit line from the sensing node using the bit line select circuit to apply a bit line bias voltage to the remaining bit lines;
- and
- outputting the program data that are latched in the latch circuit to the selected bit line through the sensing node in response to a program control signal using a second switch of each of the plurality of page buffers.
Dependencies are inferred from the claim text.