Non-volatile memory and method with compensation for source line bias errors

In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, said memory device, comprising:

• a page source line coupled to the source of each memory cell in a page;
• an aggregate node coupled to individual page source lines;
• a source voltage control circuit coupled via said aggregate node to a page source line of a selected page for memory operation;
• an associated bit line coupling to the drain of each memory cell of said page;
• and
• a bit line voltage supply for providing a predetermined bit line voltage to the associated bit line of each memory cell of said page for sensing operation, wherein each said predetermined bit line voltage is referenced with respect to said aggregate node so as not to be affected by any voltage differences between said aggregate node and a ground reference.

In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, a method of sensing a page of memory cells, comprising:

• providing a page source line;
• coupling the source of each memory cell of said page to said page source line;
• switching said page source line to a source voltage control circuit for sensing operation;
• coupling the drain of each memory cell of said page to an associated bit line;
• and
• providing a predetermined bit line voltage to the associated bit line of each memory cell of said page for sensing operation, wherein each said predetermined bit line voltage is referenced with respect to said page source line of said page so as not to be affected by any voltage differences between the page source line and a ground reference.

In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, said memory device, comprising:

• a page source line coupled to the source of each memory cell in a page;
• a page source line multiplexor;
• a source voltage control circuit coupled via said page source line multiplexor to a page source line of a selected page for memory operation;
• an associated bit line coupling to the drain of each memory cell of said page;
• and
• a bit line voltage supply for providing a predetermined bit line voltage to the associated bit line of each memory cell of said page for sensing operation, wherein each said predetermined bit line voltage is referenced with respect to said page source line so as not to be affected by any voltage differences between said page source line and a ground reference.