Test mode for detecting a floating word line
AssigneeInfineon Technologies AG
InventorNorbert Rehm
Life of this patent
Estimating the term…
Abstract
Devices and methods that allow floating word lines in memory arrays to be detected are provided. By driving local word lines from each side with divided drive lines, local word lines on one side of the memory array may be set to an predetermined voltage level (e.g., an intermediate voltage level between VPP and VNWLL). After disconnecting the local word lines on the one side, memory cells on the other side may be tested for read failures, which may indicate floating word lines on the one side.
Claims22
A method for detecting floating word lines in a dynamic random access memory device having at least one memory array, wherein voltage levels are applied to word lines of different side segments of the array by different drive and reset lines, comprising:
- forcing one or more first word lines in a first side segment of the memory array to an intermediate voltage level between a word line high voltage level and a negative word line low voltage level;
- applying the negative word line voltage level to one or more reset lines of the first side segment coupled to the first word lines via one or more pull-down transistors to bring the one or more first word lines in the first side segment to the negative word line voltage level;
- and
- accessing one or more memory cells on a second side segment of the memory array to detect a read failure indicative of one of the first word lines not being properly connected to the reset line via one of the pull-down transistors during application of the negative word line voltage level to the one or more reset lines.
A method of testing a memory device with a memory array having at least first and second side segments, wherein word lines in the first side segment are driven by different drive and reset lines than the word lines in the second side segment, comprising:
- driving word lines in both the first and second side segments in a substantially similar manner, via the different drive and reset lines, when the memory device is in a first mode;
- and
- driving word lines in the first and second side segments independently of each other, via the different drive and reset lines, when the memory device is in a second mode.
A memory array, comprising:
- first and second sets of one or more master word lines on corresponding first and second side segments of the array;
- for each master word line, a plurality of local word lines, each coupled with at least one memory cell;
- one or more common bit lines coupled to memory cells on both the first and second side segments;
- and
- divided drive and reset lines allowing local word lines on the first side segment to be driven to different voltage level than corresponding local word lines on the second side segment.
A memory device, comprising:
- a memory array having first and second side segments, each segment comprising a plurality of word lines, one or more common bit lines coupled to memory cells accessible via word lines in both the first and second side segments, and at least first and second drive and reset lines allowing word lines in the first and second side segments, respectively, to be driven to different voltage levels;
- and
- control circuitry configured to:
- drive, via one or more drive lines of the first drive lines of the first side segment, a first one or more word lines in the first side segment to an intermediate voltage level between a word line high voltage level and a negative word line low voltage level;
- apply the negative word line voltage level to one or more reset lines of the first reset lines of the first side segment, coupled to the first word lines via one or more pull-down transistors;
- and
- access one or more memory cells on a second side segment of the memory array to detect a read failure indicative of one of the first word lines not being properly connected to the reset line via one of the pull-down transistors.
A test system, comprising:
- a memory device having at least one memory array with first and second side segments, each segment comprising a plurality of word lines, one or more common bit lines coupled to memory cells accessible via word lines in both the first and second side segments, and at least first and second pairs of drive and reset lines allowing word lines in the first and second side segments to be driven to different voltage levels independently;
- and
- a tester programmed to test the device by placing the memory device in a test mode wherein the memory device is configured to force one or more first word lines in the first side segment of the memory array to an intermediate voltage level between a word line high voltage level and a negative word line low voltage level, apply the negative word line voltage level to one or more reset lines of the first side segment coupled to the first word lines via one or more pull-down transistors, and access one or more memory cells on a second side segment of the memory array.
A memory device, comprising:
- a first memory means for storing data;
- a second memory means for storing data, wherein memory cells in the first and second memory means are coupled to shared sets of sense amplifiers via bit lines;
- activation means for activating the first memory means;
- first drive means coupled to the first memory means for driving the word line means to an intermediate voltage level between a word line high voltage level and a negative word line low voltage level;
- first reset means for applying the negative word line voltage level to the activation means via one or more pull-down transistors;
- and
- detection means for accessing the second memory means and detecting floating activation means characterized by a defective connection between pull-down transistors and the activation means.
Dependencies are inferred from the claim text.