Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYeu-Der Chih
Life of this patent
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Abstract
Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and a two transistor cell where the program transistor has an extra implant to raise the Vt of the transistor to protect against punch-through disturb. A method is also described to rewrite disturbed cells, which were not selected to be programmed.
Claims18
A floating gate memory array, comprising:
- a) an array of floating gate memory cells,
- b) a source line coupled to cells in a row of said array,
- c) a word line coupled to control gates of transistors of said memory cells in the row of said array,
- d) a read bit line and a program bit line connecting between said memory cells in each column of said array.
A method for re-write if disturbed, comprising:
- a) loading input address and data into a page buffer,
- b) reading out original data from an address location of an array to a page buffer,
- c) erasing said address location, verifying the erasing of said address location, and erasing bytes failing verification,
- d) programming said address location, verifying the programming of said address location, programming bytes failing programming,
- e) verifying data in unchanged portion of said address location
- f) ending if verification of unchanged portion of said address location is passed, else re-write failed locations.
15-38. (canceled)
A method for re-writing disturbed cells, comprising:
- a) a means for loading a page buffer with input addresses and data,
- b) a means for reading data from a memory location into said page buffer,
- c) a means for erasing said address location and re-erasing those bytes failing verification of said erasing,
- d) a means for programming said memory location and re-programming those bytes failing verification of said programming,
- e) a means for verifying data in unchanged portion of said memory location and ending process if verification is true, else return to step c) to re-program data.
Dependencies are inferred from the claim text.