Circuitry for use in current switching a magnetic cell

A magnetic memory comprising:

• a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a magnetic storage element capable of being programmed by a write current driven through the magnetic storage element;
• a bit line corresponding to the plurality of magnetic storage cells;
• a plurality of word lines, each of the plurality of word lines corresponding to a magnetic storage cell of the plurality of magnetic storage cells and for allowing current to flow through the magnetic storage cell;
• bit line read/write logic corresponding to the bit line, the bit line read/write logic further including a first NAND gate having a first output, a second NAND gate having a second output, and a third NAND gate having a third output, and wherein the plurality of inverters further includes a first inverter having a first input coupled to the first output, a second inverter having a second input coupled to the second output, and a third inverter having a third input coupled to the third output, the second NAND gate or the third NAND gate providing a low signal during a write if the bit line is selected and a high signal otherwise, the first NAND gate providing a low signal if the bit line is selected during a read and a high signal otherwise;
• and
• a plurality of transistors corresponding to the bit line, the plurality of transistors being controlled by the bit line read/write logic to selectively provide a read current or the write current to the plurality of magnetic storage elements, the plurality of transistors including a first P channel transistor, a second P channel transistor, a third P channel transistor, a first N channel transistor, a second N channel transistor, and a third N channel transistor, the second P channel transistor controlled by the second NAND gate, the first N channel transistor controlled by the third inverter, the second N channel transistor controlled by the first inverter, the third P channel transistor controlled by the third NAND gate, the third N channel transistor controlled by the second inverter, and the first P channel transistor controlled by the first NAND gate, the second P channel transistor and the third N channel transistor being configured to selectively provide the read current through the plurality of magnetic storage cells in a first direction, the third P channel transistor and the second N channel transistor configured to selectively provide the write current through the plurality of magnetic storage cells in a second direction different from the first direction, the first P channel transistor and the second N channel transistor configured to provide the read current through the plurality of magnetic storage cells.

A method for utilizing a magnetic memory, the magnetic memory including a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a magnetic storage element capable of being programmed by a write current driven through the magnetic storage element, the magnetic memory also including the comprising:

• utilizing bit line read/write logic corresponding to the bit line to select a bit line of a plurality of bit lines, the bit line corresponding to a first portion of the plurality of magnetic storage cells;
• selecting at least one of a plurality of word lines, each of the plurality of word lines corresponding to a second portion of the plurality of magnetic storage cells and for allowing current to flow through at least one of the second portion of the plurality of magnetic storage cells if a corresponding bit line is selected;
• and
• selectively providing a read current or the write current to the plurality of magnetic storage elements using a plurality of switches for the bit line, the plurality of switches being controlled by the bit line read/write logic.