Individual I/O modulation in memory devices
AssigneeMicron Technology, Inc.
InventorsMehul Nagrani, Victor Wong, Jeffrey Wright
Life of this patent
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Abstract
A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The out/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
Claims18
1-17. (canceled)
A column output delay circuit for a memory device comprising:
- a first delay device for delaying a column enable signal to a first sense amplifier of said memory device for a first period of time based on a capacitance of a first input/output signal line;
- and
- a second delay device for delaying a column enable signal to a second sense amplifier of said memory device for a second period of time, different from said first period of time, based on a capacitance of a second input/output signal line.
A column output delay circuit for a memory device comprising:
- a first delay device and a second delay device,
- wherein said first delay device is coupled to a first sense amplifier,
- wherein said first sense amplifier is coupled to a first input/output line having a first capacitance,
- wherein said second delay device is coupled to a second sense amplifier,
- wherein said second sense amplifier is coupled to a second input/output line having a second capacitance.
A memory device comprising:
- a memory array;
- a first sense amplifier coupled to the memory array by a first input/output signal line, said first input/output signal line having a first capacitance;
- a second sense amplifier coupled to the memory array by a second input/output signal line, said second input/output signal line having a second capacitance;
- and
- a column output delay circuit comprising a first delay device coupled to provide a column enable signal to said first sense amplifier and a second delay device coupled to provide a column enable signal to said second sense amplifier.
A processor system comprising:
- a processor;
- and
- a memory device, said memory device comprising:
- a memory array,
- a first sense amplifier coupled to the memory array by a first input/output signal line, said first input/output signal line having a first capacitance,
- a second sense amplifier coupled to the memory array by a second input/output signal line, said second input/output signal line having a second capacitance, and
- a column output delay circuit comprising a first delay device coupled to said first sense amplifier and a second delay device coupled to said second sense amplifier, said first and second delay devices causing said first and second sense amplifiers to operate at different times.
Dependencies are inferred from the claim text.