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US 2006/0221670 A1Published application
In-service reconfigurable DRAM and flash memory device
AssigneeMicron Technology, Inc.
InventorsLeonard Forbes, Paul Farrar
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsLeonard Forbes, Paul Farrar
Estimating the term…
A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. One gate is a polysilicon gate and gate insulator that is adjacent to the floating body of the transistor and acts as a DRAM cell. The non-volatile memory cell is constructed on the other side of the pillar with a floating gate or NROM structure. The DRAM and non-volatile cells are linked by a drain region coupling the two cells to a memory array bitline. The bottom of trenches on either side of the pillar have source regions that are linked to respective source lines of the memory array.
A method for operating a memory array in a DRAM mode, the array comprising a plurality of vertical memory cells each having a DRAM cell and a non-volatile memory cell, the DRAM cell having a source region, a drain region coupled to an array bitline, and a control gate coupled to a DRAM wordline, the non-volatile memory cell comprising a source region, a drain region, and a control gate coupled to a non-volatile memory wordline, the method comprising:
A method for operating a memory array in a DRAM mode, the array comprising a plurality of vertical memory cells each having a DRAM cell and a non-volatile memory cell, the DRAM cell having a source region, a drain region coupled to an array bitline, and a control gate coupled to a DRAM wordline, the non-volatile memory cell comprising a source region, a drain region, and a control gate coupled to a non-volatile memory wordline, the method comprising:
A method for operating a memory array in a non-volatile memory mode, the array comprising a plurality of vertical memory cells each having a DRAM cell and a non-volatile memory cell, the DRAM cell having a source region, a drain region, and a control gate coupled to a DRAM wordline, the non-volatile memory cell comprising a source region, a drain region coupled to an array bitline, and a control gate coupled to a non-volatile memory wordline, the method comprising:
A method for operating a memory array comprising a plurality of vertically structured memory cells each having a DRAM cell and a non-volatile memory cell, the DRAM cell having a source region, a drain region, and a control gate coupled to a DRAM wordline, the non-volatile memory cell comprising a source region, a drain region coupled to an array bitline, and a control gate coupled to a non-volatile memory wordline, the method comprising:
A method for operating a memory array comprising a plurality of vertically structured memory cells each having a DRAM cell and a non-volatile memory cell, the DRAM cell having a source region, a drain region, and a control gate coupled to a DRAM wordline, the non-volatile memory cell comprising a source region, a drain region coupled to an array bitline, and a control gate coupled to a non-volatile memory wordline, the method comprising:
Dependencies are inferred from the claim text.