Semiconductor memory device for low voltage

Abstract

A semiconductor memory device includes a first cell block having a plurality of unit cells for providing a data signal included in a unit cell through a corresponding bit line pair; a plurality of bit line sense amplifying blocks for sensing and amplifying the data signal delivered to the corresponding bit line pair by using the power supply voltage and a low voltage which is lower than the ground voltage; a decoding unit for generating a plurality of decoding signals to provide the plurality of decoding signals into the plurality of bit line sense amplifying blocks respectively in order to deliver the sensed and amplified data signal to a data line; and a low voltage generation unit for generating the low voltage by using a parasitic capacitor generated at a signal line of the decoding signal as a storing capacitor.

Dependencies are inferred from the claim text.