US 2006/0221664 A1 · Semiconductor memory device for a low voltage operation

Abstract

A semiconductor memory device maintains a same operation speed, without a use of high voltage, even when a driving voltage is low (e.g., below 1.0V). In particular, the inventive semiconductor memory device can reduce a leakage current in a bit line sense amp unit at a low voltage. For this, the semiconductor memory device of the invention comprises a first cell array for applying a data signal onto a first bit line or a first bit line bar, a first reference cell block for applying a reference signal onto the first bit line bar when the data signal is inputted to the first bit line, or the reference signal to the first bit line bar when the data signal is inputted to the first bit line bar, a second cell array for applying the data signal onto a second bit line or a second bit line bar, a second reference cell block for applying the reference signal onto the second bit line bar when the data signal is inputted to the second bit line, or the reference signal to the second bit line bar when the data signal is inputted to the second bit line bar, and a bit line sense amp for sensing and amplifying a difference of data signals applied onto one pair of bit lines that are connected to the sense amp out of a pair of the first bit lines and a pair of the second bit lines, wherein each bit line maintains a floating state without an input of an extra pre-charge voltage upon a pre-charge operation, and the other pair of the bit lines that are not connected to the sense amp are pre-charged with the reference signal by the corresponding reference cell block.

Claims35

Dependent claims

A semiconductor memory device with a folded bit line structure, which is operative by an input of a supply voltage and a ground voltage, comprising:

a first cell array for applying a data signal onto a first bit line or a first bit line bar;
a first reference cell block for applying a reference signal onto the first bit line bar when the data signal is inputted onto the first bit line, or the reference signal onto the first bit line bar when the data signal is inputted onto the first bit line bar;
a second cell array for applying the data signal onto a second bit line or a second bit line bar;
a second reference cell block for applying the reference signal onto the second bit line bar when the data signal is inputted onto the second bit line, or the reference signal onto the second bit line bar when the data signal is inputted onto the second bit line bar;
and
a bit line sense amp for sensing and amplifying a difference of the data signals applied onto one pair of bit lines that are connected to the sense amp, out of a pair of the first bit lines or a pair of the second bit lines,
wherein each bit line maintains a floating state without an input of a separate pre-charge voltage upon a pre-charge operation, and the other pair of the bit lines that are not connected to the sense amp are pre-charged with the reference signal by the corresponding reference cell block.

4 more elements

A driving method for use in a semiconductor memory device having a folded bit line structure, which is operative by an input of a supply voltage and a ground voltage, of sensing and amplifying a difference of voltage levels of signals applied to a first bit line and a first bit line bar that are connected to a first cell array arranged on one side of a bit line sense amp, or to a second bit line and a second bit line bar that are connected to a second cell array provided on the other side of the bit line sense amp, the method comprising the steps of:

connecting the fist bit line and the first bit line bar to the bit line sense amp and disconnecting the second bit line and the second bit line bar from the bit line sense amp;
activating unit cell selected among a plurality of unit cells provided in the first cell array and transferring a data signal stored in the unit cell to the first bit line;
applying a reference signal onto the first bit line bar;
sensing, and amplifying, and latching a difference of data signals on the first bit line and the bit line bar using the ground voltage and a low voltage whose absolute value is lower than the ground voltage by the bit line sense amp;
and
maintaining voltage levels on the second bit line and the second bit line bar connected to the second cell array at a pre-charge level, during an interval where the first cell array is connected to the bit line sense amp.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device for a low voltage operation

Life of this patent

Semiconductor memory device for a low voltage operation

Life of this patent

Abstract

Claims35