Memory controller, image processing controller, and electronic instrument
AssigneeSeiko Epson Corporation
InventorsTetsuo Kawamoto, Toshiyuki Yamamoto
Life of this patent
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AssigneeSeiko Epson Corporation
InventorsTetsuo Kawamoto, Toshiyuki Yamamoto
Estimating the term…
A memory controller including: a rectangular area designation register which is used for designating a rectangular area inside a display area; an address generation circuit which generates an address of the memory corresponding to a position of each pixel inside the rectangular area; a color designation register in which designated pixel data is designated; and a bit block transfer control register. When the bit block transfer is enabled, the memory controller writes the designated pixel data in the memory based on the address generated by the address generation circuit corresponding to a bit block transfer rectangular area. When the bit block transfer is disabled, the memory controller writes input pixel data in the memory based on the address generated by the address generation circuit corresponding to an input pixel data transfer rectangular area.
A memory controller which is used for writing pixel data into a memory, the memory controller comprising:
Dependencies are inferred from the claim text.