Memory interface control circuit
AssigneeNEC Corporation
InventorMutsumi Aoki
Life of this patent
Estimating the term…
Abstract
The memory interface control circuit includes a mask-release-signal generation circuit which generates a basic mask-release signal from a data strobe signal input from a DRAM and a read timing signal indicative of a read start, a mask-release-signal generation circuit which generates a mask signal from a basic mask-release signal and a read mode signal indicative of a read mode of the DRAM, and a strobe signal generation circuit which generates an internal data strobe signal from a delayed data strobe signal and the mask signal. The mask of the data strobe signal alleviates gridge noise in the memory interface control circuit
Claims4
A memory interface control circuit for use in a memory controller for reading data from a double-data-rate synchronous DRAM (SDRAM), comprising:
- a basic-mask-release-signal generation circuit for generating a basic mask-release signal based on a data strobe signal generated in the SDRAM and a read mode signal indicating a read mode of the SDRAM;
- a delay circuit for delaying the data strobe signal to generate a delayed data strobe signal;
- an internal data-strobe-signal generation circuit for generating an internal data strobe signal based on the delayed data strobe signal and the basic mask-release signal;
- and
- a latch circuit for latching read data based on the internal data strobe signal.
Dependencies are inferred from the claim text.