US 2006/0221043 A1Published application

Display

AssigneeSanyo Epson Imaging Devices Corporation

InventorsHiroyuki Horibata, Michiru Senda

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Abstract

A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. This display comprises a shift register circuit including a logic composition circuit portion constituted of a plurality of first conductive type transistors turned on with a first voltage supply source for receiving a first shift signal and a second shift signal and outputting a shift output signal by logically compositing the first shift signal and the second shift signal with each other. At least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting the first shift signal or the second shift signal to a second voltage supply source not turning on the transistors of the logic composition circuit portion in response to a prescribed drive signal.

Claims16

Dependent claims

A display comprising a shift register circuit including:

a first shift register circuit portion outputting a first shift signal;
a second shift register circuit portion arranged subsequently to said first shift register circuit portion for outputting a second shift signal;
and
a logic composition circuit portion, constituted of a plurality of first conductive type transistors turned on with a first voltage supply source, receiving said first shift signal and said second shift signal and outputting a shift output signal by logically compositing said first shift signal and said second shift signal with each other, wherein
at least either said first shift register circuit portion or said second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting said first shift signal or said second shift signal to a second voltage supply source not turning on said transistors of said logic composition circuit portion in response to a prescribed drive signal.

2 more elements

Dependencies are inferred from the claim text.