Display device
AssigneePanasonic Corporation
InventorsKazuhito Tanaka, Akio Niwa, Mitsuhiro Kasahara, Tadayuki Masumori, Mamoru Seike
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Abstract
A test pattern generation circuit (100) outputs a test pattern (TP) during a clock phase adjustment period. A flip-flop circuit (110) latches the test pattern (TP) at the fall of a shift clock (SCK) and outputs it as a test pattern (Tpa). A latch miss detection circuit (130) outputs a latch miss detection signal (LM) indicating presence/absence of a latch miss generation according to the test pattern (TPa) and a delay shift clock (DSCK). A clock phase control section (120) delays the shift clock (SCK) according to the latch miss detection signal (LM), thereby outputting a delay shift clock (DSCK).
Claims24
A display device comprising:
- a plurality of discharge cells;
- a clock signal generator that generates a clock signal;
- a serial data generator that generates serial data according to an image to be displayed;
- a test signal generator that generates a test signal;
- a data driver that selectively applies a drive pulse to said plurality of discharge cells based on the serial data generated by said serial data generator in synchronization with said clock signal in a write period for selecting the discharge cell to be lighted;
- a latch failure detector that detects the presence/absence of a latch failure in said data driver based on the test signal generated by the test signal generator in a period other than said write period;
- and
- a phase adjusting device that when the latch failure is detected by said latch failure detector, adjusts the phase of the clock signal provided from said clock signal generator to said data driver, based on the phase of the clock signal in which the latch failure is detected.
Dependencies are inferred from the claim text.