High density row ram for column parallel cmos image sensors
AssigneeMicron Technology, Inc.
InventorGraham Kirsch
Life of this patent
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Abstract
A readout circuit of an imager that enables analog-to-digital converters (ADCs) to be shared between columns of the imager is provided. Groups of ADCs share a single block of memory for storing signals processed by the ADCs. The ADCs process signals received from one group of columns of pixels and, at a different time, the ADCs process signals from another group of columns of pixels. While one of the signals processed from a column is being stored in a first memory bank, signals previously processed and stored in a second memory bank are being readout of the storage locations and provided downstream for further processing.
Claims36
A readout circuit for an imaging device, comprising:
- an analog-to-digital conversion circuit coupled to receive pixel signals from a plurality of columns of a pixel array;
- and
- a memory selectively coupled to said analog-to-digital circuit having a plurality of memory locations for respectively storing digital signals representing signals on said plurality of columns of said pixel array,
- wherein said plurality of memory locations further comprises at least first and second memory locations which are adapted to be mutually exclusively enabled at a time for a write operation.
(canceled)
A readout circuit for a CMOS imaging device, comprising:
- a plurality of analog-to-digital conversion circuits each coupled to a plurality of column lines of a pixel array;
- and
- first and second memory banks comprising at least some of a plurality of memory locations for respectively storing digital data representing analog signal values on said column lines.
(canceled)
A readout circuit for a CMOS imaging device, comprising:
- a plurality of analog-to-digital conversion circuits each circuit coupled to a plurality of column lines of a pixel array and a plurality of memory locations for respectively storing digital data representing analog signal values on said column lines,
- each circuit being respectfully coupled to an associated first column of pixels and an associated second column of pixels in a pixel array;
- and
- a ramp signal generator coupled to said plurality of analog-to-digital conversion circuits, said generator providing a common ramp comparison signal to each analog-to-digital conversion circuit.
A method of reading out signals from a pixel array, comprising:
- selectively coupling an analog-to-digital conversion circuit to and receiving analog pixels signals from a plurality of columns of pixels in a pixel array;
- selectively coupling said analog-to-digital conversion circuit to and providing digital representations of said analog pixels signals to a plurality of memory locations in a memory such that said digital representations of pixels associated with one column of said array are written in a first group of memory locations and said digital representations of pixels associated with another column of said array are written in a second group of memory locations, and
- enabling said first group of memory locations for a write operation in which said digital representations are written in a first group of memory locations and at substantially the same time enabling a second group of memory locations for a read out operation in which said second group of memory locations storing said digital representation are read out.
(canceled)
A method of reading out signals from a pixel array, comprising:
- processing a first pixel signal from a first pixel in first column of pixels;
- storing said first processed pixel signal in a first memory location associated with an analog-to-digital circuit;
- processing a second pixel signal from a second pixel in second column of pixels;
- storing said second processed pixel signal in a second memory location associated with said analog-to-digital circuit;
- and
- enabling said first memory location for writing at substantially the same time enabling said second memory location for reading.
A method of reading out signals from a pixel array, comprising:
- reading a first plurality of analog pixel signals from a first plurality of columns of pixels;
- providing a common ramp comparison signal;
- and
- comparing in respective plurality of comparator circuits said first plurality of analog signals with said common ramp comparison signal and providing respective logic signals indicating the results of said comparisons.
A method of forming a pixel array, comprising the steps of:
- forming a pixel array over a substrate;
- forming a plurality of comparator circuits over said substrate, each comparator circuit selectively coupled to first and second columns of pixels in said pixel array;
- and
- forming a two memory banks over said substrate, each memory bank having a memory location selectively coupled to one of said comparator circuits.
An integrated circuit, comprising:
- a pixel array;
- a readout circuit coupled to said pixel array, comprising:
- an analog-to-digital conversion circuit coupled to receive pixel signals from a plurality of columns of a pixel array;
- and
- a memory selectively coupled to said analog-to-digital circuit having a plurality of memory locations for respectively storing digital signals representing signals on said plurality of columns of said pixel array,
- wherein said plurality of memory locations further comprises at least first and second memory locations which are adapted to be mutually exclusively enabled at a time for a write operation.
(canceled)
Dependencies are inferred from the claim text.