Apparatus and related method for level clamping control
AssigneeMStar Semiconductor, Inc.
InventorsKe-Chiang Huang, Ta-Chan Kao, Sterling Smith
Life of this patent
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AssigneeMStar Semiconductor, Inc.
InventorsKe-Chiang Huang, Ta-Chan Kao, Sterling Smith
Estimating the term…
A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.
A level clamping control circuit for clamping an input signal, comprising:
A method for level clamping an input signal, comprising:
Dependencies are inferred from the claim text.