Apparatus and method for reducing interference
AssigneeSilicon Laboratories Inc.
InventorAugusto Marques
Life of this patent
Estimating the term…
Abstract
A method and apparatus is provided for use in an integrated circuit or printed circuit board for reducing or minimizing interference. An inductance is formed using two or more inductors coupled together and configured such that current flows through the inductors in different directions, thus at least partially canceling magnetic fields. When designing a circuit, the configuration of the inductors, as well as the relative positions of portions of the circuit, can be tweaked to provide optimal interference or noise control.
Claims20
A circuit formed on an integrated circuit comprising:
- an inductance formed by first and second conductive loops coupled together, the first and second conductive loops defining a first axis extending through the first and second conductive loops and defining a second axis perpendicular to the first axis, wherein the first and second conductive loops are configured such that current flows in opposite directions in the first and second loops to at least partially cancel magnetic fields generated from the loops, and such that magnetic cancellation is maximized at locations along the second axis;
- and
- digital circuitry formed on the integrated circuit, wherein the relative positions of the digital circuitry on the integrated circuit is configured to achieve a desired amount of magnetic cancellation.
A method of minimizing interference between RF circuitry and digital circuitry on an integrated circuit comprising:
- forming an inductance on the integrated circuit using first and second conductive loops coupled together, the first and second conductive loops defining a first axis extending through the first and second conductive loops and defining a second axis perpendicular to the first axis;
- configuring the first and second conductive loops such that current flows in opposite directions in the first and second loops to at least partially cancel magnetic fields generated from the loops, and such that magnetic cancellation is maximized at locations along the second axis;
- and
- configuring the relative positions of the inductance and circuitry on the integrated circuit to achieve a desired amount of magnetic cancellation.
A method of minimizing interference between an inductor formed in a first portion of an integrated circuit and a parasitic inductance formed by conductive traces in a second portion of the integrated circuit, the method comprising:
- forming the inductor in the first portion using first and second conductive loops coupled together such that current flows in opposite directions in the first and second conductive loops to at least partially cancel magnetic fields generated from the first and second conductive loops;
- and
- configuring one or more of the conductive traces in the second portion of the integrated circuit to form at least third and fourth loops such that current flows in opposite directions in the third and fourth loops to at least partially cancel magnetic fields generated from the third and fourth loops.
Dependencies are inferred from the claim text.