Controlling circuit for controlling operating clock and/or driving voltage of logic circuit, and method thereof

A controlling circuit for controlling an operating clock of a logic circuit in an electronic device, comprising:

• a storage device, for storing a first threshold value and a first return value, the first threshold value being different from the first return value;
• a detector, for detecting a system load of the electronic device to generate a detection value;
• at least one comparator, coupled to the storage device and the detector, for comparing the detection value with the first threshold value or the first return value, wherein when the detection value decreases to reach the first threshold value, the comparator generates a first indication signal, and then when the detection value increases to reach the first return value, the comparator generates a second indication signal;
• and
• a controller, coupled to the comparator, for enabling underclocking of the logic circuit when receiving the first indication signal, and disabling underclocking of the logic circuit when receiving the second indication signal.

A method for controlling an operating clock of a logic circuit in an electronic device, comprising:

• providing a storage device for storing a first threshold value and a first return value, the first threshold value being different from the first return value;
• detecting a system load of the electronic device to generate a detection value;
• comparing the detection value with the first threshold value or the first return value, wherein when the detection value increases to reach the first threshold value, generating a first indication signal, and then when the detection value decreases to reach the first return value, generating a second indication signal;
• and
• enabling overclocking of the logic circuit in accordance with the first indication signal, and disabling overclocking of the logic circuit in accordance with the second indication signal.

A method for controlling an operating clock of a logic circuit in an electronic device, comprising:

• providing a storage device for storing a first threshold value and a first return value, the first threshold value being different from the first return value;
• detecting a system load of the electronic device to generate a detection value;
• comparing the detection value with the first threshold value or the first return value, wherein when the detection value decreases to reach the first threshold value, generating a first indication signal, and then when the detection value increases to reach the first return value, generating a second indication signal;
• and
• enabling underclocking of the logic circuit in accordance with the first indication signal, and disabling underclocking of the logic circuit in accordance with the second indication signal.