Power consumption reduction circuit for clock network
AssigneeFujitsu Limited
InventorsKazufumi Komura, Takayoshi Nakamura, Keiichi Fujimura, Masahito Hirose, Keigo Nakashima, Masaki Nagato
Life of this patent
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Abstract
A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.
Claims20
A power consumption reduction circuit for use in a clock network including a power supply and a buffer circuit group for transmitting a clock signal, the power consumption reduction circuit comprising:
- a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal;
- and
- a switch circuit, connected between the buffer circuit group and the power supply, for disconnecting the buffer circuit group and the power supply when the transmission control circuit interrupts the clock signal.
A clock network for use with a power supply, the clock network comprising:
- a buffer circuit group for transmitting a clock signal;
- a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal;
- and
- a switch circuit, connected between the buffer circuit group and the power supply, for disconnecting the buffer circuit group and the power supply when the transmission control circuit interrupts the clock signal.
Dependencies are inferred from the claim text.