Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias

A method for generating a signal having a desired phase between a phase of two applied input signals, comprising:

• delaying a clock signal to generate at least two interpolation signals each having an associated phase;
• varying the slope of each of said at least two interpolation signals based on a bias signal that is varied based on a data rate of said at least two interpolation signals;
• and
• processing said at least two interpolation signals to generate an interpolated clock signal.

An integrated circuit, comprising:

• a phase interpolator, comprising:
• at least one delay element to generate at least two interpolation signals each having an associated phase;
• a variable slope unit associated with each of said at least two interpolation signals, wherein a slope of each of said variable slope units is controlled by a bias signal and wherein said slope is varied based on a data rate of said at least two interpolation signals;
• and
• an interpolator to process said at least two interpolation signals to generate an interpolated clock signal.