Data latch circuit of semiconductor device

A data latch circuit for latching a data signal in synchronization with a clock signal, comprising:

• a hold time delay unit for generating a delayed clock signal by delaying the clock signal for a hold time of the data signal;
• a data input control unit for generating a data input signal by receiving the data signal at an activation period of the delayed clock signal;
• and
• a data latch unit for latching a data signal which corresponds to the data input signal.

A method for latching a data signal in a semiconductor device, comprising the steps of:

• a) generating a delayed clock signal by delaying a clock signal for a hold time;
• b) starting to latch the data signal at a first transition timing of the data signal while the delayed clock signal is at a first level;
• and
• c) finishing the latch of the data signal at a second transition timing of the data signal while the delayed clock signal is at a second level.