Clock generator and clock duty cycle correction method
AssigneeHynix Semiconductor Inc.
InventorHwang Hur
Life of this patent
Estimating the term…
Abstract
A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock to thereby output comparing signal; a DCC controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal and a first and a second lock state signal; a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate a rising and a falling pre-clock signals; and a clock selector for selectively output the rising and the falling pre-clock signals in response to the weight selection signal.
Claims13
An apparatus for correcting clock duty cycle, comprising:
- a phase comparator for comparing a phase of a rising clock with that of a falling clock to output a comparing signal;
- a clock duty cycle correction (DCC) controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal;
- a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate rising and falling pre-clock signals;
- and
- a clock selector for selectively outputting the rising and the falling pre-clock signals in response to the weight selection signal.
A method for correcting clock duty cycle, comprising:
- comparing a phase of a rising clock with that of a falling clock to thereby output a comparing signal;
- outputting a clock duty cycle correction (DCC) enable signal and a weight selection signal in response to the comparing signal and a first and a second lock state signal;
- blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate rising and falling pre-clock signals;
- and
- selectively output the rising and the falling pre-clock signals in response to the weight selection signal.
A clock duty cycle correction (DCC) circuit for correcting clock duty cycle, comprising:
- a phase comparator for comparing a phase of a rising clock with that of a falling clock to output a comparing signal;
- a DCC controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal and a first and a second lock state signal;
- a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate rising and falling pre-clock signals;
- and
- a clock selector to selectively output the rising and the falling pre-clock signals in response to the weight selection signal.
Dependencies are inferred from the claim text.