Delay locked loop device

A delay locked loop device comprising:

• an input connection that receives an input clock signal that is to be delayed;
• an output connection that provides a delayed output clock signal;
• a delay device comprising a controllable delay time, a first circuit part, a second circuit part that is connected downstream in a signal flow direction from the first circuit part, and a third circuit part that is connected downstream in a signal flow direction from the second circuit part, wherein the delay device is connected in series between the input connection and the output connection;
• a control device that provides a control signal to the delay device, wherein the control signal is determined by a phase difference between the input clock signal and the delayed output clock signal;
• wherein:
• the first circuit part is configured to receive and reduce the frequency of the input clock signal so as to produce a clock signal at a reduced frequency to that of the input clock signal;
• the second circuit part is configured to receive the clock signal at the reduced frequency and delay the clock signal at the reduced frequency by a controllable delay time so as to produce a clock signal at the reduced frequency and a delayed time to that of the input clock signal;
• the third circuit part is configured to receive and reconstruct the clock signal at the reduced frequency and the delayed time such that the output clock signal is at the frequency of the input clock signal.