Flip-flop circuit having low power data retention

The flip-flop circuit of 14, wherein the second coupling means comprises:

• a first switch having a first signal terminal coupled to the input/output terminal, a second signal terminal coupled to the input of the first inverting circuit, and a control input for receiving a power down signal;
• a second switch having a first signal terminal coupled to the input/output terminal, a second signal terminal, and a control input for receiving a clock signal;
• and
• a third switch having a first signal terminal coupled to the second signal terminal of the second switch, a second signal terminal coupled to the output of the second inverting circuit, and a control input for receiving the power down signal.

A flip-flop comprising a master latch having an output coupled to a slave latch,

• wherein power is removed from the master latch during a power down mode, wherein the master latch comprises a first plurality of transistors, at least one transistor of the first plurality of transistors having a first gate dielectric thickness, the slave latch comprising:
• an input/output terminal;
• coupling means comprising a second plurality of transistors, at least one transistor of the second plurality of transistors having a second gate dielectric thickness that is greater than the first gate dielectric thickness;
• and
• a pair of inverters selectively coupled together by the coupling means to latch a signal received from the master latch through the input/output terminal during a portion of a normal mode of operation and all of the power down mode of operation, wherein the pair of inverting circuits comprises a third plurality of transistors having the second gate dielectric thickness;
• and
• an output circuit, coupled to the input/output terminal, comprising a plurality of transistors having the first gate dielectric thickness.