Multiple reference clock synthesizer
AssigneeFreescale Semiconductor, Inc.
InventorCinda Flynn
Life of this patent
Estimating the term…
Abstract
A clock synthesizer for dividing a source clock by N.R including a logic circuit, a delay line, a select circuit, an accumulator, and a clock divider circuit. The logic circuit divides N.R by 2M to get NNEW.RNEW in which NNEW is zero and RNEW is at least 0.5. The delay line receives a first clock and has multiple delay taps, where the first clock is based on the source clock. The select circuit selects the delay taps based on a tap select value and provides a delayed clock. The accumulator adds RNEW for each cycle of the delayed clock and performs a modulo function on a sum value to generate the tap select value. The clock divider circuit transitions an output clock based on selected transitions of the delayed clock, which is achieved by dividing the first clock or the delayed clock by 2M−1.
Claims20
A clock synthesizer that divides a source clock by a fractional divide ratio N.R which is at least one, comprising:
- a logic circuit which determines an integer M such that the fractional divide ratio N.R divided by 2M provides a new digital value NNEW.RNEW in which said NNEW value is zero and said RNEW value is at least 0.5;
- a delay line having an input receiving a first clock and having a plurality of delay taps, wherein said first clock has a frequency which is the frequency of the source clock divided by a first value;
- a select circuit having a plurality of selectable inputs coupled to said plurality of delay taps, a select input receiving a tap select value, and an output providing a delay clock;
- an accumulator which adds said RNEW value to a sum value for each cycle of said delay clock and that performs a modulo function on said sum value to generate said tap select value;
- and
- a first clock divider circuit that transitions an output clock based on selected transitions of said delay clock wherein said transitions are selected to divide the frequency of the delay clock by a second value in which said first value multiplied by said second value is 2M.
A clock synthesizer that divides a source clock by a binary fractional divide ratio N.R which is at least one, comprising:
- a logic circuit which right shifts N.R an integer number M times to provide a new digital value NNEW.RNEW in which said NNEW value is zero and in which a most significant bit of said RNEW value is 1;
- a delay line having an input receiving a first clock and having a plurality of delay taps, wherein said first clock has a frequency which is the frequency of the source clock divided by a first value;
- a select circuit having a plurality of selectable inputs coupled to said plurality of delay taps, a select input receiving a tap select value, and an output providing a second clock;
- an accumulator which adds said RNEW value to a sum value for each cycle of said second clock and that performs a modulo function on said sum value to generate said tap select value;
- and
- a clock counter circuit that transitions an output clock based on selected transitions of said second clock wherein said transitions are selected to divide the frequency of the second clock by a second value in which the first value multiplied by the second value is 2M.
A method of dividing a source clock by a fractional divide ratio N.R which is at least one, comprising:
- dividing determining an integer M such that the fractional divide ratio N.R divided by 2M provides a new digital value NNEW.RNEW in which the NNEW value is zero and the RNEW value is at least 0.5;
- providing a free-running first clock through a delay line having a plurality of delay taps, wherein the first clock has a frequency that is the frequency of the source clock divided by a first value;
- selecting one of the plurality of delay taps based on a tap select signal and providing a delayed clock based on selected delay taps;
- accumulating the RNEW value for each cycle of said delayed clock to a sum value;
- performing a modulo function of the sum value to generate the tap select signal;
- and
- transitioning an output clock based on selected transitions of the delayed clock wherein the transitions are selected to divide the delayed clock by a second value in which the first and second values multiplied together is 2m.
Dependencies are inferred from the claim text.