Semiconductor device with level conversion circuit
AssigneeNEC Electronics Corporation
InventorHiromu Katou
Life of this patent
Estimating the term…
Abstract
A level conversion circuit includes a differential pair of first and second transistors receiving differential input signals; a current mirror section; and a CMOS-type latch circuit. The current mirror section includes a first current mirror circuit receiving output current from the first transistor to output a first mirror current; a second current mirror circuit receiving output current of the second transistor to output a second mirror current; a third current mirror circuit receiving the second mirror current to output a third mirror current to a first output terminal of differential output terminals; and a fourth current mirror circuit receiving the first mirror current to output a fourth mirror current to a second output terminal of the differential output terminals.
Claims13
A level conversion circuit comprising:
- differential pair transistors configured to receive differential input signals;
- a current mirror section connected to outputs of said differential pair transistors and configured to output mirror currents to differential output terminals;
- and
- first and second inverters cross-coupled to each other between said differential output terminals.
Dependencies are inferred from the claim text.