Differential blocking sampler, in particular for an analog digital converter

Abstract

The invention relates to a blocking sampler intended in particular to be used upstream of a fast analog digital converter. The blocking sampler comprises two main semi-samplers each having a respective differential input (E, E′) and a respective differential output (S, S′). With each main semi-sampler is associated a respective auxiliary blocking semi-sampler comprising an auxiliary tracking transistor (T1a, T1a′) powered by a voltage tapped off from the terminals of the storage capacitor (C′, C) of the other main blocking sampler, an auxiliary storage capacitor (Ca, Ca′) linked to the output of this auxiliary tracking transistor and an auxiliary current switch (T2a, T3a, SC1a; T2′a, T3′a, SC1a′) controlled in synchronism with the current switch of the main blocking sampler so as to authorize or block the passage of current in the auxiliary tracking transistor. The auxiliary samplers serve to improve the sampling dynamics in the cases where the signal to be sampled varies rapidly.

Dependencies are inferred from the claim text.