Sample-hold circuit and semiconductor device
AssigneeSharp Kabushiki Kaisha
InventorHiroyuki Hirashima
Life of this patent
Estimating the term…
Abstract
A first sampling capacitor 3 is connected between an output terminal of a first analog switch 1 and the ground, and an input terminal of a second analog switch 2 is connected to a node between the first analog switch 1 and the first sampling capacitor 3. A second sampling capacitor 4 is connected between an output terminal of the first analog switch 1 and the ground. A control part turning on the first and second analog switches 1 and 2 in a state in which an input voltage is applied to the input terminal of the first analog switch 1, thereafter turns off the second analog switch 2, subsequently turns off the first analog switch 1 and subsequently turns on the second analog switch 2.
Claims9
A sample-hold circuit comprising:
- a first analog switch;
- a first sampling capacitor connected between an output terminal of the first analog switch and a ground;
- a second analog switch whose input terminal is connected to a node between the first analog switch and the first sampling capacitor;
- a second sampling capacitor connected between an output terminal of the second analog switch and the ground;
- and
- a control section for performing first control for turning on the first and second analog switches, thereafter performing second control for turning off the second analog switch in a state in which the first analog switch is on, subsequently performing third control for turning off the first analog switch in a state in which the second analog switch is off and subsequently performing fourth control for turning on the second analog switch in a state in which the first analog switch is off.
Dependencies are inferred from the claim text.