Buffer circuit with current limiting
AssigneeAgere Systems Inc.
InventorsSamuel Khoo, John Kriz, Bernard Morris
Life of this patent
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Abstract
A buffer circuit is configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal. In a first mode, the buffer circuit is configured to provide a low output impedance, characteristic of a digital buffer. In a second mode, the buffer circuit is configured to limit an output current of the buffer circuit. The control signal is indicative of a level of the output signal of the buffer circuit.
Claims20
A buffer circuit configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal, wherein in a first mode the buffer circuit is configured to provide a low output impedance, and in a second mode the buffer circuit is configured to limit an output current of the buffer circuit, the control signal being indicative of a level of the output signal of the buffer circuit.
An integrated circuit including at least one buffer circuit, the at least one buffer circuit being configurable to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal, wherein in a first mode the buffer circuit is configured to provide a low output impedance, and in a second mode the buffer circuit is configured to limit an output current of the buffer circuit, the control signal being indicative of a level of the output signal of the buffer circuit.
Dependencies are inferred from the claim text.