Low power scan design and delay fault testing technique using first level supply gating

A circuit containing a logic block under testing, the circuit comprising:

• an input block containing a plurality of latches, the latches connected serially such that an output of one of the latches is connected to an input of a successive latch;
• and
• a combinatorial logic block containing a plurality of logic gates, the plurality of logic gates including first level gates connected to the input block, at least one of the first level gates containing:
• first means for providing at least one of a virtual ground and virtual power supply to the first level gate, and
• second means for providing the virtual ground or virtual power supply to an output of the first level gate.

A method of testing a logic block, the method comprising:

• sequentially loading a sequence of signals to a plurality of latches in an input block;
• providing the sequence to first level gates in a combinatorial logic block directly from the input block once the sequence is completely loaded into the latches;
• preventing propagation through the combinatorial logic block of input signals from the input block before the sequence is completely loaded;
• and
• capturing output signals from the combinatorial logic block once the sequence is provided to the first level gates.

A system containing a logic block under testing, the system comprising:

• an input block containing a plurality of latches, the latches connected serially such that an output of one of the latches is connected to an input of a successive latch;
• a combinatorial logic block containing a plurality of logic gates, the plurality of logic gates including first level gates connected to the input block, a plurality of the first level gates having at least one first switch through which the first level gates are disconnected from a supply voltage and ground, the first level gates each having a switching circuit connected to an output of the first level gate and including a second switch;
• a clock circuit that supplies a clock signal to the input block;
• a timing control circuit that supplies a control signal to the input block and the combinatorial logic block, the control signal controlling the first and second switches;
• and
• a detector to capture an output from the combinatorial logic block in response to a predetermined sequence of signals supplied from the latches to the combinatorial logic block.