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US 2006/0220675 A1Published application
Transmission line driver
AssigneeFreescale Semiconductor, Inc.
InventorsDivya Tripathi, Qadeer Khan, Kulbhushan Misri
Life of this patent
Estimating the term…
Abstract
A transmission line driver with slew rate control includes high and low side ramp generators for generating charge and discharge ramp signals, respectively, which are input to respective comparators and a pair of source follower transistors. A pair of additional transistors is connected to the pair of source follower transistors and a pair of staggered drivers is connected to the pair of additional transistors.
Claims17
A transmission line driver with slew rate control, comprising:
- a high side ramp generator that receives a speed signal and a data signal and generates a charge ramp signal;
- a low side ramp generator that receives the speed signal and the data signal and generates a discharge ramp signal;
- a first comparator having a first input that receives the charge ramp signal, a second input that receives a first reference voltage signal, and a first comparator output signal;
- a second comparator having a first input that receives the discharge ramp signal, a second input that receives a second reference voltage signal, and a second comparator output signal;
- an NMOS source follower transistor having a gate connected to the high side ramp generator and receiving the charge ramp signal, and a drain connected to a first voltage level;
- a PMOS source follower transistor having a gate connected to the low side ramp generator and receiving the discharge ramp signal, a drain connected to a ground, and a source connected to a source of the NMOS source follower transistor, wherein a node between the sources of the NMOS and PMOS source follower transistors is an output node;
- a pair of additional drivers including a PMOS transistor having a gate connected to the first comparator and receiving the first comparator output signal, and a source connected to the first voltage level, and a NMOS transistor having a gate connected to the second comparator and receiving the second comparator output signal, a source connected to the ground, and a drain connected to a drain of the PMOS additional transistor and the output node;
- and
- a pair of staggered drivers including a PMOS transistor having a gate connected to the first comparator and receiving the first comparator output signal, a source connected to the first voltage level, and a drain connected to the output node, and a NMOS transistor having a gate connected to the second comparator and receiving the second comparator output signal, a source connected to the ground, and a drain connected to the output node.
6 more elements
A transmission line driver with slew rate control, comprising:
- a high side ramp generator that receives a speed signal and a data signal and generates a charge ramp signal;
- a low side ramp generator that receives the speed signal and the data signal and generates a discharge ramp signal;
- a first comparator having a first input that receives the charge ramp signal, a second input that receives a first reference voltage signal, and a first comparator output signal;
- a second comparator having a first input that receives the discharge ramp signal, a second input that receives a second reference voltage signal, and a second comparator output signal;
- an NMOS source follower transistor having a gate connected to the high side ramp generator and receiving the charge ramp signal, and a drain connected to a first voltage level;
- a PMOS source follower transistor having a gate connected to the low side ramp generator and receiving the discharge ramp signal, a drain connected to a ground, and a source connected to a source of the NMOS source follower transistor, wherein a node between the sources of the NMOS and PMOS source follower transistors is an output node;
- a pair of additional drivers including a PMOS transistor having a gate connected to the first comparator and receiving the first comparator output signal, and a source connected to the first voltage level, and a NMOS transistor having a gate connected to the second comparator and receiving the second comparator output signal, a source connected to the ground, and a drain connected to a drain of the PMOS additional transistor and the output node;
- and
- a pair of staggered drivers including a PMOS transistor having a gate connected to the first comparator by way of a first resistor and receiving the first comparator output signal, a source connected to the first voltage level, and a drain connected to the output node, and a NMOS transistor having a gate connected to the second comparator by way of a second resistor and receiving the second comparator output signal, a source connected to the ground, and a drain connected to the output node.
6 more elements
Dependencies are inferred from the claim text.